Questions and Answers

1. How gray code is useful in clock domain crossing.

Suppose a vector control signal Sig [2:0] crosses from Domain 1 to Domain 2. Signal Sig also decides the state of Domain 2 and you assume that the value "100" of Sig [2:0] indicates an invalid state for Domain 2. Now, think of a situation, where the signal Sig wants to change its value from "000" to "101" . This requires the two bits Sig [0] and Sig [2] to transit simultaneously. Both these transition occurs very close to the destination sampling clock edge . By virtue of meta-stability, transition on Sig [2] gets captured correctly and the transition on Sig [0] is missed. In this way,  the system moves to state "100" which is invalid.

This case would not have happened, if changing the states of the design requires changing only a single bit of the vector (Sig in this case). In case of a single bit transition, either that transition would be captured in the destination domain or not. This way the design either stays in the previous state or move to a valid state. Therefore, for vector control signals (multi-bit signals, such as address buses), the usual solution is to use a Gray code when crossing a clock domain boundary. A Gray code ensures that only a single bit changes as the bus counts up or down.

To avoid problems due to CDC , one can use fifo or 2-stage flip flop synchronizer.

2. Why pull up is used more than pull down register?
Pull up and pull down is used to remove floating state of input pin of IC. Pull up can control incoming current to input pins, so it is used more.

3. Detail about set up and hold time.

The easy way to think of setup and hold is that there is a sampling window.  This window in

time is defined by its starting time and ending time, and both of these are referenced to

the clock edge.  However the starting time of the window, or setup time, is positive when

before the clock edge, and the end of the window, or hold time is positive when after

the clock edge.  This is a historical method of defining the window and based on circuits

that typically had positive values for both setup and hold.  So here's a simple way of seeing

how the window comes in time with respect to the clock edge:

Clock edge is defined as T_0

Start of window is:  T_0 - setup

End of window is T_0 + hold

Note that setup and hold can both be negative, positive or zero.  i.e.  the sampling window can

come entirely before the clock edge (positive setup, negative hold), it can start before and

end after the clock edge (positive setup and positive hold), or it can come entirely after

the clock edge (negative setup and positive hold).

The important thing is that the sampling window should come while the input data is

stable.  If the data changes during the sampling window, there is a timing error.